1. Field
The following description relates to a computing apparatus and method of handling an interrupt, and moreover, to a technique for handling an interrupt that occurs in the process of performing a loop operation in a reconfigurable array.
2. Description of the Related Art
Typically, a reconfigurable architecture denotes an architecture that enables a hardware constitution of a computing apparatus to be optimized for each task.
Reconfigurable architecture refers the ability of underlying hardware architectures or devices to alter the functionalities of its components and the interconnection between them to perform a desired task. Reconfigurable architecture includes, for example, a reconfigurable processor, a coarse-grained array, and the like.
A reconfigurable processor may be a microprocessor with erasable hardware that can rewire itself dynamically. This allows the processor to adapt effectively to the programming tasks demanded by a particular software that the processor is attempting to interface with at any given time. For example, a reconfigurable processor can transform itself to a video chip, a central processing unit (CPU), a graphics chip, and the like.
When a task is processed in a hardware manner, it is difficult to efficiently process the task even when the task is slightly changed due to the fixed functions of the hardware. When a task is processed in a software manner, it is possible to change the functions of the software to meet the task, however, the processing can often take a greater amount of time, and the processor often runs at less efficient speed.
The reconfigurable architecture may satisfy the advantages that the hardware/software have while at the same time alleviating some of the disadvantages. In particular, reconfigurable architecture may be used in the field of processing a digital signal, for example, in a process in which the same task is repeatedly performed.
The reconfigurable architecture includes various types as mentioned above, such as the reconfigurable processor and the coarse-grained array. The coarse-grained array may consist of a plurality of processing units. Controlling connections between the processing units enables the units to be optimized for tasks.
When an interrupt occurs in the process of performing a loop operation in a coarse-grained array, handling the interrupt may become an issue. The interrupt may include a hardware interrupt, for example, an external I/O device, a timer, and the like. The interrupt may include an exception, for example, an undefined instruction, and the like. The interrupt may include a software interrupt, for example, a system call, and the like. Typically, when an interrupt occurs, the current context stored in a register while processing the interrupt is saved. The context may be use to restore the loop operation.
Because the coarse-grained array includes a plurality of register files, a large amount of overhead for processing a generated interrupt is created.